View SP6655ER-LTR_4862941.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 date: 12/23/05 sp6655 high efficiency 400ma synchronous buck regulator ?copyright 2005 sipex corporation sp6655 high efficiency 400ma synchronous buck regulator the sp6655 is a 400ma synchronous buck regulator which is ideal for portable applications that use a li-ion or 3 cell alkaline/nicd/nimh input. the sp6655? proprietary control loop, 20 a light load quiescent current, and 0.3 ? power switches provide excellent efficiency across a wide range of output currents. as the input battery supply decreases towards the output voltage, the sp6655 seamlessly transitions into 100% duty ratio operation, further extending useful battery life. the sp6655 is protected against overload and short circuit conditions with a precise inductor peak current limit. other features include programmable under voltage lockout and low battery detection, externally programmed output voltage down to 1.0v, logic level shutdown control, and 140 c over temperature shutdown. ideal for portable designs powered with li ion battery description features 98% efficiency possible small 10-pin dfn package ultra-low 20 a quiescent current 625ma inductor peak current limit guaranteed minimum 400ma output current 2.7v to 5.5v input voltage range output adjustable down to 1.0v 100% duty ratio low dropout operation 80 a light load quiescent current in dropout applications cell phones pda's dsc's mp3 players usb devices point of use power typical application schematic sp6655 10 pin dfn 10 9 8 7 6 1 2 3 4 5 p vin vin blon d1 d0 lx p gnd gnd v out fb now available in lead free packaging blon vi vo d1 d0 10 f l1 10 h v out 400ma 2.7v to 5.5v input 10 ? 1 f sp6655 p vin blon d1 d0 lx gnd v out fb p gnd v in 10 f c in cv in c out r vin r f cf 22pf r i 200k 1m
2 date: 12/23/05 sp6655 high efficiency 400ma synchronous buck regulator ?copyright 2005 sipex corporation v in =uv in =v sdn =3.6v, v out =v fb , i o = 0ma, t amb = -40 c to +85 c, typical values at 27 c unless otherwise noted. pv in ,v in .............................................................................................. 6v all other pins .............................................................. -0.3v to v in +0.3v pv in , p gnd , lx current ........................................................................ 2a storage temperature .................................................. -65 c to 150 c operating temperature ................................................. -40 c to +85 c absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. electrical characteristics parameter min typ max units conditions input voltage operating uvlo 5.5 v result of i q measurement at v in =pv in =5.5v range minimum output voltage 1.0 v fb set voltage, vr 0.784 0.800 0.816 v 25 c, i o =200ma close loop. l i = 10 h, c out = 22 f overall accuracy measured at v in =5.5v, no load and (-40 c to 85 c) 5%v in =3.6v, 200ma load, close loop (0 c to 70 c) 4 on-time constant - k on 1.5 2.25 3.0 v* s close loop, l i = 10 h,c out = 22 f min, t on =k on /(v in -v out ) off-time constant - k off 1.6 2.4 3.2 v* s inductor current limit tripped, vfb=0.5v min, t off =k off /v out measured at v out =1v off-time blanking 100 ns turn on time 200 400 s 400ma load pmos switch resistance 0.3 0.6 ? i pmos = 200ma nmos switch resistance 0.3 0.6 ? i nmos = 200ma inductor current limit 500 625 750 ma vfb=0.5v power efficiency 96 % v out =2.5v, i o =200ma 92 v out =3.3v, i o =400ma minimum guaranteed load 400 500 ma current v in quiescent current 20 30 av out =3.3v, v in =3.6v and v in = 5.5v v in shutdown current 1 500 na d1=d0=0v v out quiescent current 2 5 av out = 3.3v v out shutdown current 1 500 na d1=d0=0v uvlo 2.55 2.70 2.85 d1=0v, d0=v in undervoltage lockout 2.70 2.85 3.00 v d1=v in , d0=0v threshold, v in falling 2.85 3.00 3.15 d1=v in , d0=v in uvlo hysteresis 40 mv battlo trip voltage, v in falling 265 300 335 mv measured as v in -v out battlo trip voltage hysteresis 9 mv blon low output voltage 0.4 v v in =3.3v, i sink =1ma blon leakage current 1 av blon =3.6v over-temperature 140 c rising trip point over-temperature hysteresis 14 c d1,d0 leakage current 1 500 na d1,d0 input threshold voltage 0.60 0.90 v high to low transition 1.25 1.8 v low to high transition fb leakage current 1 100 na fb=1v lx leakage 3 5 a d1,d0=0v, v in =3.6v lx=0v,lx=v in +0.2v
3 date: 12/23/05 sp6655 high efficiency 400ma synchronous buck regulator ?copyright 2005 sipex corporation pin description pin number pin name description 1p vin input voltage power pin. inductor charging current passes through this pin. 2v in internal supply voltage. control circuitry powered from this pin. 3 blon open drain battery low output. (v in -v o ) less than 300mv pulls this node to ground. (v in -v o ) above threshold, this node is open. 4d1digital mode control input. see table i for definition. 5d0digital mode control input. see table i for definition. 6fbexternal feedback network input connection. connect a resistor from fb to ground and fb to v out to set the output voltage. this pin regulates to the internal bandgap reference voltage of 0.8v. 7v out output voltage sense pin. used by the timing circuit to set minimum on and off times. 8 gnd internal ground pin. control circuitry returns current to this pin. 9p gnd power ground pin. synchronous rectifier current returns through this pin. 10 lx inductor switching node. inductor tied between this pin and the output capacitor to create regulated output voltage. functional diagram d1 d0 00shutdown. all internal circuitry is disabled and the power switches are opened. 01device enabled, falling uvlo threshold =2.70v 10device enabled, falling uvlo threshold =2.85v 11device enabled, falling uvlo threshold =3.00v table 1. operating mode definition v in zero_x drvon qr qs min ton blon d0 p vin ovr_i min ton ovr_i k off /v out v in lx t off = uvlo blank = t blank (=100ns) or t off = k off /v out v out ilim/m ref 1 volow _ fb +- v ramp rst p gnd tsd blank +- 300mv + - c uvlo internal supply ref' ovr_i v out + - c drvon blank ilim/m d1 volow + - c t onover min t on = k on /( v in - v out ) ref one-shot drvon + - c block fb' gnd ref m +- vos driver drvon =100ns t onover
4 date: 12/23/05 sp6655 high efficiency 400ma synchronous buck regulator ?copyright 2005 sipex corporation efficiency vs load, v out = 1.5v line/load rejection, v out = 3.3v line/load rejection, v out = 1.5v no load battery current, v out =3.3v no load battery current, v out =1.5v typical performance characteristics refer to the typical application schematic, t amb = +27 c efficiency vs. load, v out =3.3v 60 65 70 75 80 85 90 95 100 0.1 1.0 10.0 100.0 1000.0 iload (ma) efficiency (%) vi=3.6v vi=3.9v vi=4.2v vi=5.0v 60 65 70 75 80 85 90 95 100 0.1 1.0 10.0 100.0 1000.0 iload (ma) efficiency (%) vi=3.6v vi=3.9v vi=4.2v vi=5.0v 3.15 3.20 3.25 3.30 3.35 3.40 3.45 0 100 200 300 400 500 iload (ma) vout (v) vi=3.6v vi=3.9v vi=4.2v vi=5.0v 1.45 1.47 1.49 1.51 1.53 1.55 0 100 200 300 400 500 iload (ma) vout (v) vi=3.6v vi=3.9v vi=4.2v vi=5.0v 0 100 200 300 400 500 3.0 3.3 3.6 3.9 4.2 vin (v) iin (ua) tamb = 85c tamb = 25c tamb = -40c 0 10 20 30 40 50 3.0 3.3 3.6 3.9 4.2 vin (v) iin ( _ __ _ a) tamb = 85c tamb = 25c tamb = -40c
5 date: 12/23/05 sp6655 high efficiency 400ma synchronous buck regulator ?copyright 2005 sipex corporation typical performance characteristics refer to the typical application schematic, t amb = +27 c efficiency at 3.3vout (l1 = lqh2mcn4r7) 50 60 70 80 90 100 0.1 1 10 100 1000 iout (ma) efficiency (%) vin=3.6v vin=4.2v 4.7uh efficiency at 3.3vout (l1 = lqh32cn4r7) 50 60 70 80 90 100 0.1 1 10 100 1000 iout (ma) efficiency (%) vin=3.6v vin=4.2v 4.7uh efficiency at 1.8vout (l1 = lqh32cn4r7) 50 60 70 80 90 100 0.1 1 10 100 1000 iout (ma) efficiency (%) vin=3.0v vin=3.6v vin=4.2v 4.7uh efficiency at 3.3vout (l1 = lqh31cn4r7) 50 60 70 80 90 100 0.1 1 10 100 1000 iout (ma) efficiency (%) vin=3.6v vin=4.2v 4.7uh efficiency at 1.8vout (l1 = lqh31cn4r7) 50 60 70 80 90 100 0.1 1 10 100 1000 iout (ma) efficiency (%) vin=3.0v vin=3.6v vin=4.2v 4.7uh efficiency at 1.8vout (l1 = lqh2mcn4r7) 50 60 70 80 90 100 0.1 1 10 100 1000 iout (ma) efficiency (%) vin=3.0v vin=3.6v vin=4.2v
6 date: 12/23/05 sp6655 high efficiency 400ma synchronous buck regulator ?copyright 2005 sipex corporation 0.0 100.0 200.0 300.0 400.0 500.0 600.0 700.0 3.5 4.0 4.5 5.0 vin (v) frequency (khz) vout = 3.3v measured vout = 3.3v calculated 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 3.6 3.9 4.2 4.5 4.8 5.1 5.4 vin (v) kon (v*usec) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 vin (v) kon (v*usec) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 3.6 3.9 4.2 4.5 4.8 5.1 5.4 vin (v) koff (v*usec) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 vin (v) koff (v*usec) k on vs v in , v out =3.3v k on vs v in , v out =1.5v k off vs v in , v out =3.3v k off vs v in , v out =1.5v typical performance characteristics refer to the typical application schematic, t amb = +27 c 0.0 100.0 200.0 300.0 400.0 500.0 600.0 700.0 3.4 3.8 4.2 4.6 5.0 vin (v) frequency (khz) vout = 1.5v measured vout = 1.5v calculated ripple frequency vs. v in , i out =0.4a, v out =3.3v ripple frequency vs. v in , i out =0.4a, v out =1.5v
7 date: 12/23/05 sp6655 high efficiency 400ma synchronous buck regulator ?copyright 2005 sipex corporation load step, v in =4.2v, i out =0.1a to 0.4a, v out =3.3v load step, v in =4.2v, i out =0.1a to 0.4a, v out =1.5v start up from shdn, v in =5v ,i out =0.4a, v out =3.3v start up from shdn, v in =5v, i out =0.4a, v out =1.5v typical performance characteristics refer to the typical application schematic, t amb = +27 c v in start up, v in =4.2v, i out =0.4a, v out =3.3v v in start up,v in =4.2v, i out =0.4a, v out =1.5v ch.1=v in 5.0v/div. ch.4=i in 0.5a/div. ch.2=v out 0.5v/div. ch.4=i lx 0.5a/div. ch.2=v out 2.0v/div. ch.1=v shdn 5.0v/div. ch.4=i lx 0.5a/div. ch.2=v out 2.0v/div. ch.1=v shdn 5.0v/div.
8 date: 12/23/05 sp6655 high efficiency 400ma synchronous buck regulator ?copyright 2005 sipex corporation theory of operation the sp6655 is a high efficiency synchro- nous buck regulator with an input voltage range of +2.7v to +5.5vand an output that is adjustable between +1.0v and v in . the sp6655 features a unique on-time control loop that runs in discontinuous conduction mode (dcm) or continuous conduction mode (ccm) using synchronous rectification. other features include over-temperature shutdown, over-current protection, digitally controlled enable and under-voltage lock- out, a battery low indicator, and an external feedback pin. the sp6655 operates with a light load qui- escent current of 20 a using a 0.3 ? pmos main switch and a 0.3 ? nmos synchro- nous switch. it operates with excellent effi- ciency across the entire load range, making it an ideal solution for battery powered ap- plications and low current step-down con- versions. the part smoothly transitions into a 100% duty cycle under heavy load/low input voltage conditions. on-time control - charge phase the sp6655 uses a precision comparator and a minimum on-time to regulate the output voltage and control the inductor cur- rent under normal load conditions. as the feedback pin drops below the regulation point, the loop comparator output goes high and closes the main switch. the minimum on-timer is triggered, setting a logic high for the duration defined by: t on = k on . v in - v out where: k on = 2.25v * sec constant v in = v in pin voltage v out = v out pin voltage to accommodate the use of ceramic and other low esr capacitors, an open loop ramp is added to the feedback signal to mimic the inductor current ripple. the fol- lowing waveforms describe the ideal ramp operation in both ccm and dcm operation. in either ccm or dcm, the negative going ramp voltage (v ramp in the functional dia- gram) is added to fb and this creates the fb's signal. this fb signal is applied to the negative terminal of the loop comparator. the ref voltage of 0.8v is applied to the positive terminal of the loop comparator plus an offset voltage vos to compensate for the dc level of v ramp applied to the negative terminal. the result is an internal ramp with enough negative going offset (approximately 50mv) to trip the loop com- parator whenever fb falls below regulation. the output of the loop comparator, a rising volow, causes a set if blank = 0 and ovr_i = 0. this starts inductor charging (drvon = 1) and starts the minimum on- timer. the minimum on-timer times out and drvon ref, fb v os ref fb i(l1) ramp: dcm operation drvon ref, fb v os ref fb i(l1) ramp: ccm operation
9 date: 12/23/05 sp6655 high efficiency 400ma synchronous buck regulator ?copyright 2005 sipex corporation indicates drvon can be reset if the voltage loop is satisfied. if v out is still below the regulation point, reset is held low until v out is above regulation. once reset occurs, t on minimum is reset, and the t off one-shot is triggered to blank the loop com- parator from starting a new charge cycle for a minimum period. this blanking period occurs during the noisy lx transition to discharge, where spurious comparator states may occur. for t off > t blank, the loop is in a discharge or wait state until the loop comparator starts the next charge cycle by drvon going high. if an over current condition occurs during charge, the loop is interrupted and drvon is reset. the off-time one-shot pulse width is widened to t off = k off / v out , which holds the loop in discharge for that time. at the end of the off-time, the loop is released and controlled by volow. in this manner maximum inductor current is controlled on a cycle-by-cycle basis. an assertion of uvlo (undervoltage lockout) or tsd (thermal shut- down) holds the loop in no-charge until the fault has ended. on-time control - discharge phase the discharge phase follows with the high side pmos switch opening and the low side nmos switch closing to provide a discharge path for the inductor current. the decreas- ing inductor current and the load current cause the output voltage to drop. under normal load conditions when the inductor current is below the programmed limit, the off-time will continue until the output voltage falls below the regulation threshold, which initiates a new charge cycle via the loop comparator. the inductor current ?loats?in continuous conduction mode. during this mode the inductor peak current is below the pro- grammed limit and the valley current is above zero. this is to satisfy load currents that are greater than half the minimum cur- rent ripple. the current ripple, i lr , is defined by the equation: i lr k on * v in - v out - i out * r ch l v in - v out where: l = inductor value i out = load current r ch = pmos on resistance, 0.3 ? typ. if the i out * r ch term is negligible compared with (v in - v out ), the above equation simpli- fies to: i lr k on l for most applications, the inductor current ripple controlled by the sp6655 is constant regardless of input and output voltage. the maximum loop frequency in ccm is de- fined by the equation: f lp ( v in - v out ) * (v out + i out * r dc ) k on * [v in + i out * (r dc - r ch )] where: f lp = ccm loop frequency r dc = nmos on resistance, 0.3 ? typ. ignoring conduction losses simplifies the loop frequency to: f lp 1 * v out * (v in - v out ) k on v in and?ng the loop comparator and the on- timer reduces the switching frequency for load currents below half the inductor ripple current. this increases light load efficiency. the minimum on-time insures that the in- ductor current ripple is a minimum of k on /l, more than the load current demands. the converter goes in to a standard pulse fre- quency modulation (pfm) mode where the switching frequency is proportional to the load current. theory of operation
10 date: 12/23/05 sp6655 high efficiency 400ma synchronous buck regulator ?copyright 2005 sipex corporation low dropout and load transient operation and?ng the loop comparator also increases the duty ratio past the ideal d= v out /v in up to and including 100%. under a light to heavy load transient, the loop comparator will hold the main switch on longer than the minimum on timer until the output is brought back into regulation. also, as the input voltage supply drops down close to the output voltage, the main mosfet resistance loss will dictate a much higher duty ratio to regulate the output. eventually as the input voltage drops low enough, the output voltage will follow, caus- ing the loop comparator to hold the con- verter at 100% duty cycle. this mode is critical in extending battery life when the output voltage is at or above the minimum usable input voltage. the dropout voltage is the minimum (v in -v out ) below which the output regulation cannot be main- tained. the dropout voltage of sp6655 is equal to i l * (0.3 ? + r l1 ) where 0.3 ? is the typical r ds(on) of the p-channel mosfet and r l is the dc resistance of the inductor. the sp6655 has been designed to operate in dropout with a light load i q of only 80 a. the on-time control circuit seamlessly op- erates the converter between ccm, dcm, and low dropout modes without the need for compensation. the converter? transient response is quick since there is no compen- sated error amplifier in the loop. inductor over-current protection to reduce the light load dropout i q , the sp6655 over-current system is only en- abled when i l1 > 400ma. the inductor over- current protection circuitry is programmed to limit the peak inductor current to 0.625a. this is done during the on-time by compar- ing the source to drain voltage drop of the pmos passing the inductor current with a second voltage drop representing the maxi- mum allowable inductor current. as the two voltages become equal, the over-current comparator triggers a minimum off-time one shot. the off-time one shot forces the loop into the discharge phase for a minimum t off time causing the inductor current to decrease. at the end of the off-time, loop control is handed back to the and? on-time signal. if the output voltage is still low, charging begins until the output is in regula- tion or the current limit has been reached again. during startup and over-load condi- tions, the converter behaves like a current source at the programmed limit minus half the current ripple. the minimum t off is controlled by the equation: t off (min) = k off v out under-voltage lockout the sp6655 is equipped with a program- mable under-voltage lockout to protect the input battery source from excessive cur- rents when substantially discharged. when the input supply is below the uvlo thresh- old, both power switches are open to pre- vent inductor current from flowing. the three levels of falling input voltage uvlo threshold have a typical hysteresis of 120mv to prevent chattering due to the impedance of the input source. during uvlo, blon is forced low. under-current detection the synchronous rectifier is comprised of an inductor discharge switch, a voltage com- parator, and a driver latch. during the off- time, positive inductor current flows into the pgnd pin 9 through the low side nmos switch to lx pin 10, through the inductor and the output capacitor, and back to pin 9. the comparator monitors the voltage drop across the discharge nmos. as the induc- tor current approaches zero, the channel theory of operation
11 date: 12/23/05 sp6655 high efficiency 400ma synchronous buck regulator ?copyright 2005 sipex corporation voltage sign goes from negative to positive, causing the comparator to trigger the driver latch and open the switch to prevent induc- tor current reversal. this circuit along with the on-timer puts the converter into pfm mode and improves light load efficiency when the load current is less than half the inductor ripple current defined by k on /l. thermal shutdown the converter will open both power switches if the die junction temperature rises above 140 c. the die must cool down below 126 c before the regulator is re-enabled. this fea- ture protects the sp6655 and surrounding circuitry from excessive power dissipation due to fault conditions. shutdown/enable control the d0, d1 pins 4,5 of the device are logic level control pins that shut down the con- verter when both are a logic low, or enable the converter when either are a logic high. when the converter is shut down, the power switches are opened and all circuit biasing is extinguished leaving only junction leak- age currents on supply pins 1 and 2. after pins 4 or 5 are brought high to enable the converter, there is a turn on delay to allow the regulator circuitry to re-establish itself. power conversion begins with the assertion of the internal reference ready signal which occurs approximately 150 s after the en- able signal is received. battery low indicator the blon function is a differential mea- surement of (v in -v out ) which causes the open drain nmos on pin 3 to sink current to ground when (v in -v out ) < 300mv. tying a resistor from pin 3 to v in or v out creates a logic level battery low indicator. a low band- width comparator and 3% hysteresis filter the input voltage ripple to prevent noisy transitions at the threshold. blon is forced low when in uvlo. external feedback pin the fb pin 6 is compared to an internal reference voltage of 0.8v to regulate the sp6655 output. the output voltage can be externally programmed within the range +1.0v to +5.0v by tying a resistor from fb to ground and fb to v out (pin7). see the applications section for resistor selection information. inductor selection the sp6655 uses a specially adapted mini- mum on-time control of regulation utilizing a precision comparator and bandgap refer- ence. this adaptive minimum on-time con- trol has the advantage of setting a constant current ripple for a given inductor size. from the operations section it has been shown: inductor current ripple, i lr k on l theory of operation application information 200ma, and would be fairly constant for differ- ent input and output voltages, simplifying the selection of components for the sp6655 power circuit. other inductor values could be se- lected, as shown in table 1 components selection. using a larger value than 10 h in an attempt to reduce output voltage ripple would reduce inductor current ripple and may not produce as stable an output ripple. for larger inductors with the sp6655, which has a peak inductor current of 0.625a, most 15 h or 22 h inductors would have to be of larger physical sizes, limiting their use in small portable applications. smaller values for the typical sp6655 application circuit with inductor size of 10 h, and k on of 2v* sec, the sp6655 current ripple would be about
12 date: 12/23/05 sp6655 high efficiency 400ma synchronous buck regulator ?copyright 2005 sipex corporation sp6655 compselect oct-05.xls series r isat manufacturer ohms (a) l x w (mm) ht . (mm) website 4.7 murata lqh32cn4r7m53l 0.150 0.65 3.2x2.5 1.55 www.murata.com 4.7 murata lqh31cn4r7m03l 0.65 0.34 3.2x1.6 1.8 www.murata.com 4.7 murata lqh2mcn4r7m02l 0.80 0.30 2.0x1.6 0.9 www.murata.com 10 murata lqh32cn100k53l 0.300 0.45 3.2x2.5 1.55 www.murata.com 10 tdk rlf5018t-100mr94 0.056 0.94 5.6x5.2 2.0 www.tdk.com 10 coilcraft lpo6013-103k 0.300 0.70 6.0x5.4 1.3 www.coilcraft.com 22 murata lqh32cn220k21 0.710 0.25 3.2x2.5 2.0 www.murata.com 22 tdk rlf5018t-220mr63 0.130 0.63 5.6x5.2 2.0 www.tdk.com 22 coilcraft lpo6013-223k 0.520 0.45 6.0x5.4 1.3 www.coilcraft.com esr ripple current voltage capacitor manufacturer ohms (max) (a) @ 45c l x w (mm) ht. (mm) (v) type website 10 tdk c2012x5r0j106m 0.003 1.00 2.0x1.2 1.25 6.3 x5r ceramic www.tdk.com 10 murata grm21br60j106ke01 0.003 1.00 2.0x1.2 1.25 6.3 x5r ceramic www.murata.com 4.7 tdk c2012x5r0j475m 0.005 1.00 2.0x1.2 1.25 6.3 x5r ceramic www.tdk.com 4.7 murata grm21br60j475ke01 0.005 1.00 2.0x1.2 1.25 6.3 x5r ceramic www.murata.com note: components highlighted in bold are those used on the sp6655 evaluation board. inductors - surface mount capacitors - surface mount capacitance (uf) inductance (uh) size inductor type size capacitor specification manufacturer/part no. manufacturer/part no. inductor specification unshielded ferrite core unshielded ferrite core shielded ferrite core unshielded ferrite core unshielded ferrite core unshielded ferrite core shielded ferrite core unshielded ferrite core unshielded ferrite core table 1 component selection resistance should be chosen for high effi- ciency designs. recommended inductors with low dc resistance are listed in table 1. preferred inductors for on board power sup- plies with the sp6655 are magnetically shielded types to minimize radiated magnetic field emissions. capacitor selection the sp6655 has been designed to work with very low esr output capacitors (listed in table 1 component selection) which for the typical application circuit are 10 f ceramic capacitors. these capacitors combine small size, low esr and good value. to regulate the output with low esr capacitors of 0.01 ? or less, an internal ramp voltage v ramp has been added to the fb signal to reliably trip the loop comparator (as described in the operations section). the output capacitor is required to keep the output voltage ripple small and to ensure regulation loop stability. the output capaci- tor must have low impedance at the switch- ing frequency. ceramic capacitors with x5r application information like 10 h would more easily meet the 0.625a limit and come in small case sizes, and the increased inductor current ripple of almost 200ma would produce very stable regula- tion and fast load transient response at the expense of slightly reduced efficiency. other inductor parameters are important, such as the inductor current rating and the dc resistance. when the current through the inductor reaches the level of i sat , the induc- tance drops to 70% of the nominal value. this non-linear change can cause stability prob- lems or excessive fluctuation in inductor cur- rent ripple. to avoid this, the inductor should be selected with saturation current at least equal to the maximum output current of the converter plus half the inductor current ripple. to provide the best performance in dynamic conditions such as start-up and load tran- sients, inductors should be chosen with satu- ration current close to the sp6655 inductor current limit of 0.625a. dc resistance, another important inductor characteristic, directly affects the efficiency of the converter, so inductors with minimum dc
13 date: 12/23/05 sp6655 high efficiency 400ma synchronous buck regulator ?copyright 2005 sipex corporation application information or x7r dielectrics are recommended due to their low esr and high ripple current. the output ripple ? v out is determined by: ? v out <= 1 . v out * (vinmax - v out ) * { esr + (8 * osc * c out ) } ( vinmax * l * osc ) to improve stability, a small ceramic capaci- tor, c f = 22pf should be paralleled with the feedback voltage divider rf, as shown on the typical application schematic on page 1. an- other function of the output capacitance is to hold up the output voltage during the load transients and prevent excessive overshoot and undershoot. the typical performance char- acteristics curves show very good load step transient response for the sp6655 with the recommended output capacitance of 10 f ceramic. the input capacitor will reduce the peak cur- rent drawn from the battery, improve effi- ciency and significantly reduce high frequency noise induced by a switching power supply. the typical input capacitor for the sp6655 is 10 f ceramic. these capacitors will provide good high frequency bypassing and their low esr will reduce resistive losses for higher efficiency. an rc filter is recommended for the v in pin 2 to effectively reduce the noise for the ic's analog supply rail which provides power to sensitive circuits. this time constant needs to be at least 5 times greater than the switching period, which is calculated as 1/flp during the ccm mode. the typical applica- tion schematic uses the values of r vin = 10 ? and c vin = 1 f to meet these requirements. output voltage program the output voltage is programmed by the external divider, as shown in the typical appli- cation circuit on page 1. first pick a value for r i that is no larger than 300k ? . too large a value of r i will reduce the ac voltage seen by the loop comparator, since the internal fb pin capacitance can form a low pass filter with r f in parallel with r i . the formula for r f with a given r i and output voltage is: r f = ( v out - 1 ) ?r i 0.8v output voltage ripple frequency an important consideration in a power sup- ply application is the frequency value of the output ripple. given the control technique of the sp6655 (as described in the operations section), the frequency of the output ripple will vary when in light to moderate load in the discontinuous or pfm mode. for mod- erate to heavy loads greater than about 100ma inductor current ripple, (for the typi- cal 10 h inductor application on 100ma is half the 200ma inductor current ripple), the output ripple frequency will be fairly con- stant. from the operations section, this maximum loop frequency in continuous conduction mode is: 1 . v out ( v in - v out ) f lp k on * v in * data for loop frequency, as measured from output voltage ripple frequency, can be found in the typical performance curves. layout considerations proper layout of the power and control circuits is necessary in a switching power supply to obtain good output regulation with stability and a minimum of output noise. the sp6655 application circuit can be made very small and reside close to the ic for best performance and solution size, as long as some layout techniques are taken into consideration. to avoid excessive interference between the sp6655 high frequency converter and the other active components on the board, some rules should be followed. refer to the typical application schematic on page 1 and the sample pcb layout shown in the following figures to illustrate how to layout a sp6655 power supply.
14 date: 12/23/05 sp6655 high efficiency 400ma synchronous buck regulator ?copyright 2005 sipex corporation application information avoid injecting noise into the sensitive part of circuit via the ground plane. input and output capacitors conduct high frequency current through the ground plane. sepa- rate the control and power grounds and connect them together at a single point. power ground plane is shown in the figure titled pcb top sample layout and connects the ground of the c out capacitor to the ground of the c in capacitor and then to the pgnd pin 10. the control ground plane connects from pin 9 gnd to ground of the c vin capacitor and the r i ground return of the feedback resistor. these two separate control and power ground planes come together in the figure titled pcb top sample layout where sp6655 pin 9 gnd is con- nected to pin 10 pgnd. power loops on the input and output of the converter should be laid out with the short- est and widest traces possible. the longer and narrower the trace, the higher the resistance and inductance it will have. the length of traces in series with the capaci- tors increases their esr and esl and reduces their effectiveness at high frequen- cies. therefore, put the 1 f bypass ca- pacitor as close to the v in and gnd pins of the converter as possible, the 10 f c in close to the p vin pin and the 10 f output capacitor as close to the inductor as pos- sible. the external voltage feedback net- work r f , r i and feedforward capacitor c f should be placed very close to the fb pin. any noise traces like the lx pin should be kept away from the voltage feedback net- work and separated from it by using power ground copper to minimize emi . sp6655 component sample layout sp6655 pc layout top side sp6655 pc layout bottom side
15 date: 12/23/05 sp6655 high efficiency 400ma synchronous buck regulator ?copyright 2005 sipex corporation package: 3 x 3 10 pin dfn min nom max min nom max a 0.80 0.90 1.00 0.032 0.036 0.039 a1 0.00 0.02 0.05 0.000 0.001 0.002 a3 k 0.20 - - 0.008 - - 0 - 14 0 - 14 b 0.18 0.25 0.30 0.008 0.010 0.012 d d2 2.20 - 2.70 0.087 - 0.106 e e2 1.40 - 1.75 0.056 - 0.069 e l 0.30 0.40 0.50 0.012 0.016 0.020 3x3 10 pin dfn jedec mo-229 variation veed-5 dimensions in millimeters: controlling dimension dimensions in inches conversion factor: 1 inch = 25.40 mm 3.00 bsc 0.119 bsc symbol sipex pkg signoff date/rev: jl aug09-05 / reva 0.20 ref 0.008 ref 0.119 bsc3.00 bsc 0.020 bsc0.50 bsc (a3) a1 a seating plane side view 10 12345 9876 index area (d/2 x e/2) bottom view b e l k d2 e2 e2/2 d2/2 pin1 designator to be within this index area (d/2 x e/2) top view d e e/2 d/2
16 date: 12/23/05 sp6655 high efficiency 400ma synchronous buck regulator ?copyright 2005 sipex corporation corporation analog excellence sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 part number operating temperature range package type sp6655er .. .................................................-40 c to +85 c ................................... (3 x 3mm) 10 pin dfn sp6655er/tr...............................................-40 c to +85 c .................................... (3 x 3mm) 10 pin dfn sp6655eu .. .................................................-40 c to +85 c .................................................. 10 pin msop sp6655eu/tr...............................................-40 c to +85 c .................................................. 10 pin msop /tr = tape and reel pack quantity is 2,500 for dfn. available in lead free packaging. to order add "-l" suffix to part number. example: sp6655er/tr = standard; sp6655er-l/tr = lead free ordering information

▲Up To Search▲

Price & Availability of SP6655ER-LTR

	To Download SP6655ER-LTR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .